A central processing unit (CPU) that executes instructions out-of-order utilizes issue logic to clear instructions for passage to the CPU's execution unit(s). This issue logic can be divided into a number of discrete components that perform aspects of the issue clearance. An instruction scoreboard is used by the issue logic to weigh the register resource requirements of each instruction in an instruction queue to ultimately prioritize the instructions for issuance. Instructions waiting in the instruction queue are represented as flat bit vectors in the scoreboard logic. Each bit represents a register of the CPU and is set, or not, based on whether the associated instruction utilizes the register. Request logic identifies which instructions in the instruction queue are ready to issue to the execution units. Finally, an arbiter actually selects the instructions for issue based upon information derived by the scoreboard and request logic.
In older CPU architectures, the arbiter circuit merely had to select one instruction for issue per cycle. In these CPUs, there was typically one integer and one floating point execution unit, with separate instruction queues.
More modern CPUs utilize multiple, parallel execution units to maximize the number of instructions that can issue per machine cycle. These architectures complicate somewhat the design of the arbiter. Not only must it be possible to execute the two instructions simultaneously based upon the register requirements, for example, but if two arbiters are used to select the two instructions for issue, the two arbiters must coordinate their mutual operation to ensure that the same instruction is not sent to different execution units. This of course wastes compute resources since the multiple execution units will be duplicating each others work.
One solution to this problem is to a priori assign each instruction in the instruction queue to issue to one or the other of the execution units. One of the arbiters is then assigned to select from the instructions to issue to one execution unit, and the other arbiter is assigned to select instructions to issue in the other execution unit.